In recent years, new microprocessing technologies have been developed along with high-level integration and performance enhancement of large scale integration (LSI). Chemical mechanical polishing (CMP) methods constitute one class of such technologies, and chemical mechanical polishing is a technology that is frequently utilized for the flattening of an interlayer insulating film, formation of a metal plug, and formation of embedded wiring (damascene wiring) in an LSI production process, particularly a multilayer wiring forming process.
This CMP has been applied to various processes in the manufacture of semiconductor devices, and one of such processes may be, for example, application to a gate forming process in transistor production. During transistor production, there are occasions in which polishing of materials such as metals, silicon, silicon oxide, polycrystalline silicon (polysilicon), and silicon nitride is needed, and depending on the structure of transistors, it is required to control the polishing rates for various materials.
For example, in recent years, films having lower dielectric constants and lower strength (Low-k films) are used. This is because since the distance between wirings is close in high-end devices, when an insulating film having a high dielectric constant is used, electrical defects may occur between wirings. However, since such Low-k films have very low strength, there has been a problem that the films are polished away to an excessive degree at the time of processing by CMP. Thus, there has been a demand for a technology, by which at the time of polishing a barrier layer, the polishing speed for a film to be polished can be maintained at a high level, while the polishing speed for a Low-k film can be sufficiently suppressed.
A technology that meets such a demand is disclosed in Patent Literature 1. Patent Literature 1 discloses a polishing composition including an oxidizing agent and a nonionic compound having a weight average molecular weight of 1,000 or less.